1. Field of the Invention
The present disclosure generally relates to the field of fabricating semiconductor devices, and more particularly, to process control and monitoring techniques for manufacturing processes on the basis of optical measurement strategies.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of semiconductor fabrication, since, here, it is essential to combine cutting-edge technology with volume production techniques. It is, therefore, the goal of semiconductor manufacturers to reduce the consumption of raw materials and consumables while at the same time improve product quality and process tool utilization. The latter aspect is especially important since, in modern semiconductor facilities, equipment is required which is extremely cost-intensive and represents the dominant part of the total production costs. For example, in manufacturing modern integrated circuits, several hundred individual processes may be necessary to complete the integrated circuit, wherein failure in a single process step may result in a loss of the complete integrated circuit. This problem is even exacerbated in current developments striving to increase the size of substrates, on which a moderately high number of such integrated circuits are commonly processed, so that failure in a single process step may possibly entail the loss of a large number of products.
Therefore, the various manufacturing stages have to be thoroughly monitored to avoid undue waste of man power, tool operation time and raw materials. Ideally, the effect of each individual process step on each substrate would be detected by measurement and the substrate under consideration would be released for further processing only if the required specifications, which would desirably have well-understood correlations to the final product quality, were met. A corresponding process control, however, is not practical, since measuring the effects of certain processes may require relatively long measurement times, frequently ex situ, or may even necessitate the destruction of the sample. Moreover, immense effort, in terms of time and equipment, would have to be made on the metrology side to provide the required measurement results. Additionally, utilization of the process tool would be minimized since the tool would be released only after the provision of the measurement result and its assessment. Furthermore, many of the complex mutual dependencies of the various processes are typically not known, so that an a priori determination of respective “optimum” process specifications may be difficult.
The introduction of statistical methods, also referred to as statistical process control (SPC), for adjusting process parameters, significantly relaxes the above problem and allows a moderate utilization of the process tools while attaining a relatively high product yield. Statistical process control is based on the monitoring of the process output to thereby identify an out-of-control situation, wherein a causality relationship may be established to an external disturbance. After occurrence of an out-of-control situation, usually operator interaction is required to manipulate a process parameter to return to an in-control situation, wherein the causality relationship may be helpful in selecting an appropriate control action. Nevertheless, in total, a large number of dummy substrates or pilot substrates may be necessary to adjust process parameters of respective process tools, wherein tolerable parameter drifts during the process have to be taken into consideration when designing a process sequence, since such parameter drifts may remain undetected over a long time period or may not be efficiently compensated for by SPC techniques.
Recently, a process control strategy has been introduced and is continuously being improved, allowing enhanced efficiency of process control, desirably on a run-to-run basis, while requiring only a moderate amount of measurement data. In this control strategy, the so-called advanced process control (APC), a model of a process or of a group of interrelated processes, is established and implemented in an appropriately configured process controller. The process controller also receives information including pre-process measurement data and/or post-process measurement data as well as information related, for instance, to the substrate history, such as type of process or processes, the product type, the process tool or process tools in which the products are to be processed or have been processed in previous steps, the process recipe to be used, i.e., a set of required sub-steps for the process or processes under consideration, wherein, possibly, fixed process parameters and variable process parameters may be contained, and the like. From this information and the process model, the process controller determines a controller state or process state that describes the effect of the process or processes under consideration on the specific product, thereby permitting the establishment of an appropriate parameter setting of the variable parameters of the specified process recipe to be performed with the substrate under consideration.
Although significant advances in providing enhanced process control strategies have been made, process variations may nevertheless occur during the complex interrelated manufacturing sequences, which may be caused by the plurality of individual process steps, which may affect the various materials in a more or less pronounced manner. These mutual influences may finally result in a significant variability of material characteristics, which in turn may then have a significant influence on the final electrical performance of the semiconductor device under consideration. Due to the continuous shrinkage of critical feature sizes, at least in some stages of the overall manufacturing process, frequently, new materials may have to be introduced to adapt device characteristics to the reduced feature sizes. One prominent example in this respect is the fabrication of sophisticated metallization systems of semiconductor devices in which advanced metal materials, such as copper, copper alloys and the like, are used in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 and significantly less, in which case these materials may also be referred to as ultra low-k dielectrics (ULK). By using highly conductive metals, such as copper, the reduced cross-sectional area of metal lines and vias may at least partially be compensated for by the increased conductivity of copper compared to, for instance, aluminum, which has been the metal of choice over the last decades, even for sophisticated integrated devices. On the other hand, the introduction of copper into semiconductor manufacturing strategies may be associated with a plurality of problems, such as sensitivity of exposed copper surfaces with respect to reactive components, such as oxygen, fluorine and the like, the increased diffusion activity of copper in a plurality of materials typically used in semiconductor devices, such as silicon, silicon dioxide, a plurality of low-k dielectric materials and the like, copper's characteristic of generating substantially no volatile byproducts on the basis of typically used plasma-enhanced etch processes, and the like. For these reasons, sophisticated inlaid or damascene process techniques have been developed in which typically the dielectric material may have to be patterned first in order to create trenches and via openings, which may then be coated by an appropriate barrier material followed by the deposition of the copper material. Consequently, a plurality of highly complex processes, such as the deposition of sophisticated material stacks for forming the interlayer dielectric material including low-k dielectrics, patterning the dielectric material, providing appropriate barrier and seed materials, filling in the copper material, removing any excess material and the like, may be required for forming sophisticated metallization systems wherein the mutual interactions of these processes may be difficult to assess, in particular, as material compositions and process strategies may frequently change in view of further enhancing overall performance of the semiconductor devices. Consequently, a thorough monitoring of the material characteristics may be required during the entire manufacturing sequence for forming sophisticated metallization systems in order to efficiently identify process variations, which may typically remain undetected despite the provision of sophisticated controlling and monitoring strategies, as described above.
With reference to FIGS. 1a-1b, typical process strategies of monitoring the characteristics of dielectric materials may be described in accordance with typical conventional process strategies.
FIG. 1a schematically illustrates a semiconductor device 100 in a manufacturing stage in which one or more material layers 110 are formed above a substrate 101. It should be appreciated that the substrate 101 may represent any appropriate carrier material for forming thereon and therein respective circuit elements, such as transistors, capacitors and the like, as may be required by the overall configuration of the device 100. The one or more material layers 110 may be formed at any appropriate manufacturing stage, for instance during a sequence for forming circuit elements in the device layer, i.e., in and above a semiconductor layer (not shown), or may be formed in the contact level or metallization level of the device 100. In the example shown in FIG. 1a, it may be assumed that the one or more material layers 110 may comprise a plurality of dielectric materials 110A, 110B, 110C which may, for instance, represent a complex material system as may be required for forming respective circuit elements or any other device features. For example, the dielectric layer 110A may represent a material, such as silicon dioxide, polycrystalline silicon and the like, which may be patterned on the basis of the layers 110B, 110C, which may represent an anti-reflective coating (ARC) layer and a photoresist material and the like. Thus, the material composition of the individual layers 110A, 110B, 110C may have a significant influence during the further processing of the device 100 and on the finally obtained electrical performance of the device 100. For instance, the material composition of the individual layers 110B, 110C may significantly affect the behavior during the lithography process for patterning the layer 110A. For instance, the index of refraction and the absorbance of the layers 110C, 110B and 110A with respect to an exposure wavelength may result in a certain optical response of the layers 110, which may be adjusted on the basis of the layer thickness of the individual layers 110. Consequently, during the deposition of the layers 110A, 110B, 110C, a respective process control may be applied so as to reduce process variations, which may result in an undesired variation of the material composition, while also the thickness of individual layers 110A, 110B, 110C may be controlled in order to maintain overall process quality. For this purpose, non-destructive optical measurement techniques are available, such as ellipsometry and the like, in which the optical thickness of the individual layers 110C, 110A, 110A may be determined, possibly after each deposition step, by using an appropriate probing optical beam 102A, which may contain any appropriate wavelength, and detecting a reflected or refracted beam 102B. Consequently, by the optical measurement process based on the beams 102A, 102B, inline measurement data may be provided to enhance process control for forming the dielectric layers 110. However, the conventionally applied optical measurement techniques may provide information about material characteristics which may vary in a more or less step-like manner, such as a pronounced change of the index of refraction at interfaces between the various layers 110A, 10B, 110C, which may be very convenient in determining the optical thickness of the materials 110 but which may not provide information with respect to a more or less gradually varying material characteristic of one or more of the layers 110. For example, it may be very difficult to determine a gradual variation within one of the layers 110 in different semiconductor devices or device areas on the basis of conventionally applied optical measurement techniques.
FIG. 1b schematically illustrates the semiconductor device 100 according to a further example in which the plurality of dielectric materials 110 may represent one or more materials of an interlayer dielectric material of a metallization system 120. For example, the layers 110 may comprise a dielectric material 110E, which may be provided in the form of a low-k dielectric material, a “conventional” dielectric material such as fluorine-doped silicon dioxide and the like, while a further dielectric material 110D may represent a low-k dielectric material, which may differ in composition from the layer 110E or which may represent substantially the same material, depending on the overall process strategy. Furthermore, as previously explained, a trench 110F may be formed in the layer 110D and a via opening 110G may be provided in the dielectric material 110E. Furthermore, in the manufacturing stage shown, a barrier layer 121 may be formed on exposed surface portions of layers 110D, 110E. For instance, the barrier layer 121 may be comprised of tantalum, tantalum nitride and the like, which are frequently used barrier materials in combination with copper.
The semiconductor device 100 as shown in FIG. 1b may be formed in accordance with well-established damascene strategies in which the layers 110E, 110D, possibly in combination with an etch stop layer 111, may be deposited by any appropriate deposition technique. During the corresponding process sequence for forming the layers 110E, 110D, optical measurement techniques may be used, for instance on the basis of the above-described concepts, in order to provide measurement data for controlling layer thickness and the like. Thereafter, the openings 110F, 110G may be formed by appropriate patterning regimes, which may involve lithography processes, resist removal processes, etch steps, cleaning steps and the like, thereby resulting in a more or less pronounced exposure of the layers 110D, 110E to various process conditions, which may have an influence on at least exposed portions of the materials 110E, 110D. For example, low-k dielectrics and in particular ultra low-k dielectric materials may be sensitive to a plurality of chemical components, which may typically be applied during the various processes, such as resist removal processes, etch processes, cleaning processes and the like. Consequently, a certain degree of material modification or damaging may occur in the layer 110D and/or the layer 110E, depending on the overall process strategy. Consequently, during the further processing, for instance by providing the barrier layer 121, the modified material composition in the dielectric material 110 may result in different process conditions and possibly also in different material characteristics of the barrier layer 121, thereby also affecting the further processing. For example, the material modification or damaging of the layer 110D may result in a reduced adhesion and/or diffusion blocking effect of the barrier material 121, which may compromise the overall reliability of the metallization system 120. In other cases, during the removal of excess material of the copper and the barrier material 121 after the electrochemical deposition of the copper material, the damaged areas of the layer 110D may have an influence on the removal conditions, which in turn may also negatively affect the overall characteristics of the resulting metallization system 120.
It is thus important to monitor respective material modifications during the process sequence for forming the metallization system 120 which, however, may be very difficult on the basis of optical inline measurement techniques, as may be used for determining characteristics such as layer thickness and the like, as previously explained with reference to FIG. 1a. The situation becomes even more complex when the material modification is to be determined for patterned devices since the patterning processes as well as the geometry of the feature elements to be formed in the layers 110 may also affect the degree of material modification, since during the patterning process a plurality of additional process conditions may be “seen” by the materials 110, which may result in a different degree of material modification compared to non-patterned structures. Since the degree of material modification may gradually vary due to even minor process variations during the complex sequence of manufacturing processes involved, in particular in patterned device structures, it may be extremely difficult to obtain a quantitative measure of the degree of damage on the basis of optical measurement techniques used in a conventional context. For this reason, frequently, external measurement techniques may be used, which may typically involve destructive analysis techniques, such as cross-sectional analysis by electron microscopy and the like, in order to obtain information on the degree of material modification within the material layers 110. However, due to the destructive nature of the analysis techniques involved, only a very limited amount of measurement data may be gathered, thereby contributing to a less efficient overall process control. Furthermore, due to the external analysis technique including sophisticated sample preparation and the like, a significant amount of delay may be involved in obtaining the measurement data, thereby also contributing to a less efficient control mechanism for the manufacturing sequence for forming the metallization system 120.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.